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Freescale Semiconductor /MK61F15WS /DDR /PAD_CTRL

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Interpret as PAD_CTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SPARE_DLY_CTRL 0RESERVED 0RESERVED0RESERVED 0RESERVED 0RESERVED 0RESERVED 0 (00)PAD_ODT_CS0 0RESERVED 0RESERVED

PAD_ODT_CS0=00

Description

I/O Pad Control Register

Fields

SPARE_DLY_CTRL

These SPARE_DLY_CTRL[3:0]bits set the delay chains in the spare logic.
RESERVED

Reserved
RESERVED

Reserved
RESERVED

Reserved
RESERVED

Reserved
RESERVED

Reserved
RESERVED

Reserved
PAD_ODT_CS0

Required to enable ODT and configure ODT resistor value in the pad.

0 (00): ODT Disabled

1 (01): 75 Ohms

2 (10): 150 Ohms

3 (11): 50 Ohms
RESERVED

Reserved
RESERVED

Reserved

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data